This application claims the benefit of Application No. P2000-7354, filed in Korea on Feb. 16, 2000, which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a nonvolatile ferroelectric memory device, and more particularly, to a driving circuit of a nonvolatile ferroelectric memory device and a method for driving the same.
2. Background of the Related Art
Generally, a nonvolatile ferroelectric memory, i.e., a ferroelectric random access memory (FRAM) has a data processing speed equal to a dynamic random access memory (DRAM) and retains data even in power off. For this reason, the nonvolatile ferroelectric memory has received much attention as a next generation memory device.
The FRAM and DRAM are memory devices with similar structures, but the FRAM includes a ferroelectric capacitor having a high residual polarization characteristic. The residual polarization characteristic permits data to be maintained even if an electric field is removed.
FIG. 1 shows a hysteresis loop of a general ferroelectric. As shown in FIG. 1, even if polarization induced by the electric field has the electric field removed, data is maintained at a certain amount (i.e., d and a states) without being erased due to the presence of residual polarization (or spontaneous polarization). A nonvolatile ferroelectric memory cell is used as a memory device by corresponding the d and a states to 1 and 0, respectively.
A related art nonvolatile ferroelectric memory device will now be described. FIG. 2 shows a unit cell of a related art nonvolatile ferroelectric memory.
As shown in FIG. 2, the related art nonvolatile ferroelectric memory includes a bitline B/L formed in one direction, a wordline W/L formed to cross the bitline, a plate line P/L spaced apart from the wordline in the same direction as the wordline, a transistor T1 with a gate connected with the wordline and a source connected with the bitline, and a ferroelectric capacitor FC1. A first terminal of the ferroelectric capacitor FC1 is connected with a drain of the transistor T1 and second terminal is connected with the plate line P/L.
The data input/output operation of the related art nonvolatile ferroelectric memory device will now be described. FIG. 3a is a timing chart illustrating the operation of the write mode of the related art nonvolatile ferroelectric memory device, and FIG. 3b is a timing chart illustrating the operation of read mode thereof.
During the write mode, an externally applied chip enable signal CSBpad is activated from high state to low state. At the same time, if a write enable signal WEBpad is applied from high state to low state, the write mode starts. Subsequently, if address decoding in the write mode starts, a pulse applied to a corresponding wordline is transited from low state to high state to select a cell.
A high signal in a certain period and a low signal in a certain period are sequentially applied to a corresponding plate line in a period where the wordline is maintained at high state. To write a logic value xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d in the selected cell, a high signal or low signal synchronized with the write enable signal WEBpad is applied to a corresponding bitline.
In other words, a high signal is applied to the bitline, and if the low signal is applied to the plate line in a period where the signal applied to the wordline is high, a logic value xe2x80x9c1xe2x80x9d is written in the ferroelectric capacitor. A low signal is applied to the bitline, and if the signal applied to the plate line is high, a logic value xe2x80x9c0xe2x80x9d is written in the ferroelectric capacitor.
The reading operation of data stored in a cell by the above operation of the write mode will now be described. If an externally applied chip enable signal CSBpad is activated from high state to low state, all of bitlines become equipotential to low voltage by an equalizer signal EQ before a corresponding wordline is selected.
Then, the respective bitline becomes inactive and an address is decoded. The low signal is transited to the high signal in the corresponding wordline according to the decoded address so that a corresponding cell is selected.
The high signal is applied to the plate line of the selected cell to destroy data corresponding to the logic value xe2x80x9c1xe2x80x9d stored in the ferroelectric memory. If the logic value xe2x80x9c0xe2x80x9d is stored in the ferroelectric memory, the corresponding data is not destroyed.
The destroyed data and the data that is not destroyed are output as different values by the ferroelectric hysteresis loop, so that a sensing amplifier senses the logic value xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d. In other words, if the data is destroyed, the xe2x80x9cdxe2x80x9d state is transited to an xe2x80x9cfxe2x80x9d state as shown in hysteresis loop of FIG. 1. If the data is not destroyed, xe2x80x9caxe2x80x9d state is transited to the xe2x80x9cfxe2x80x9d state. Thus, if the sensing amplifier is enabled after a set time has elapsed, the logic value xe2x80x9c1xe2x80x9d is output in case that the data is destroyed while the logic value xe2x80x9c0xe2x80x9d is output in case that the data is not destroyed.
As described above, after the sensing amplifier outputs data, to recover the data to the original data, the plate line becomes inactive from high state to low state at the state that the high signal is applied to the corresponding wordline.
In the aforementioned related art nonvolatile ferroelectric memory device, in case that the nonvolatile ferroelectric memory device is being used as a memory device in the system, the stable operation voltage area of the nonvolatile ferroelectric memory device and the operation voltage area of a system controller can be different.
That is, when the operation voltage area of the system controller is smaller than the operation voltage area of the nonvolatile ferroelectric memory device, the system controller generates a normal control signal at even state that the system power supply abnormally descends.
In even case that the voltage descends, the system controller is capable of operating normally, while the nonvolatile ferroelectric memory device is not capable of operating normally. Nevertheless, since the nonvolatile ferroelectric memory device reads data stored in the cell by destroying in read mode, a read cycle can be terminated before the destroyed data in the reading operation are restored at the state of abnormal descending of power supply voltage or low voltage.
Accordingly, a method for retaining data is specially required in the nonvolatile ferroelectric memory device even in reading.
For example, a method using a low voltage sensing circuit can be used as the method for retaining data.
FIG. 4 illustrates a schematic driving circuit of the related art nonvolatile ferroelectric memory device.
For reference, FIG. 4 is a circuit diagram of a low voltage sensing circuit.
As shown in FIG. 4, the related art nonvolatile ferroelectric memory device includes first transistor and second transistor T1, T2 serially connected between a power supply voltage terminal Vcc and a ground voltage terminal Vss, and the gates thereof connected with each other, a third transistor T3 controlled by output voltage of the first transistor T1 and a drain thereof connected with the ground voltage terminal Vss, a fourth transistor T4 having a source connected with the power supply voltage terminal Vcc, a drain connected with a source of the third transistor T3, and a gate connected with the ground voltage terminal Vss, a first inverter INV1 for inverting output voltage of the third transistor T3, a second inverter INV2 serially connected with the first inverter INV1 and inverting the output voltage of the third transistor T3, a third inverter INV3 for inverting output of the second inverter INV2, a fourth inverter INV4 for inverting output of the third inverter INV3 and outputting as a first output signal OUT1, a fifth inverter INV5 for inverting output signal of the first inverter INV1, a fifth transistor T5 controlled by output signal of the fifth inverter INV5, a source thereof connected with the power supply voltage terminal Vcc, a drain thereof connected with output terminal of the first inverter INV1, and a sixth inverter INV6 for inverting output signal of the fifth inverter INV5 and outputting as a second output signal OUT2.
The first, fourth, and fifth transistors T1, T4, T5 are PMOS transistors, and the second and third transistors T2, T3 are NMOS transistors.
The driving method of the related art nonvolatile ferroelectric memory device will now be described.
FIGS. 5 and 6 are operation wave diagrams of the related art driving method of the nonvolatile ferroelectric memory device. FIG. 5 illustrates the relation of an externally applied signal CSBpad and an internal chip control signal of the nonvolatile ferroelectric memory device when the system power supply descends from a normal voltage to a low voltage. FIG. 6 illustrates the relation of the signals when the system power supply ascends from a low voltage to a normal voltage.
First, as shown in FIG. 5, a first output signal OUT1 as a signal of low level, outputs a signal of low level by sensing the voltage (low voltage) of the system power supply.
A second output signal OUT2 is transited to low level after being delayed equal to Twb comparing with the first output signal OUT1 for sufficiently securing data restoration time in case that the power supply voltage ascends to a low voltage.
In such a related art nonvolatile ferroelectric memory device, regardless of an externally applied signal CSBpad, when the system power supply voltage descends to a low voltage, the first output signal OUT1 and the second output signal OUT2 are generated by using the level of the system power supply voltage for adjusting the width of the internal chip control signal, so that the time for restoring the destroyed data in the read cycle is secured to the highest degree.
As aforementioned, in the nonvolatile ferroelectric memory device, since. data becomes restored in the read cycle, data restoration becomes unstable in case of performing read operation at the state of a low voltage.
Accordingly, the internal chip control signal should be transited to low level, so that the chip does not operate.
FIG. 6 is an operation wave diagram of a low voltage sensing circuit when the system voltage ascends from a low voltage to a normal voltage.
As shown in FIG. 6, when the system voltage ascends from a low voltage to a normal voltage, a first output signal OUT1 and a second signal OUT2 are transited from low level to high level.
For reference, in FIG. 5, the second output signal OUT2 is transited after being delayed at the point which a first output signal OUT1 is transited to low level, however, the first output signal OUT1 and the second output signal OUT2 are simultaneously transited from low level to high level when the system voltage ascends from a low voltage to a normal voltage.
However, the internal chip control signal is not able to generate a normal read cycle wave in case that the system voltage returns to a normal voltage.
That is, the destroyed data is restored during the read cycle only when sufficiently securing the normral read cycle time, as shown in FIG. 5, it is impossible to restore data since the read cycle is very shortened.
Such a related art driving circuit of a nonvolatile ferroelectric memory device and a method for driving the same has the following problem.
It is impossible to stably restore the destroyed data in case that the system voltage ascends from a low voltage to a normal voltage since the read cycle is impossible to be secured, while the destroyed data can be restored by sufficiently securing the read cycle in case that the system voltage descends from a normal voltage to a low voltage.
Accordingly, the present invention is directed to a driving circuit of a nonvolatile ferroelectric memory device and a method for driving the same that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An aspect of the present invention is to provide a driving circuit of a nonvolatile ferroelectric memory device and a method for driving the same, in which the cell data are prevented from being destroyed by abnormal changes of a voltage.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. Other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description or its equivalents and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a driving circuit of a nonvolatile ferroelectric memory device according to the present invention includes: a detecting unit for detecting voltage changes of a system; a system voltage sensing signal generator for generating a low voltage sensing output or a normal voltage sensing output as a system voltage changes from a normal voltage to a lower voltage or from a lower voltage to a normal voltage; and a signal synchronization and chip control part for controlling the operation stopping or starting point of a memory cell by synchronizing output of the system voltage sensing signal generator with a chip activation signal.
In another aspect of the invention, a method for driving a nonvolatile ferroelectric memory device includes the step of synchronizing operation stopping and starting points according to changes of a system voltage from a normal voltage to a lower voltage or from a lower voltage to a normal voltage with waves of a chip activation signal.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.